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features ? fast read access time ? 120 ns automatic page write operation ? internal address and data latches for 128 bytes ? internal control timer fast write cycle time ? page write cycle time ? 10 ms maximum ? 1 to 128-byte page write operation low power dissipation ? 40 ma active current ?200 a cmos standby current hardware and software data protection data polling for end of write detection high reliability cmos technology ? endurance: 10 4 or 10 5 cycles ? data retention: 10 years single 5v 10% supply cmos and ttl compatible inputs and outputs jedec approved byte-wide pinout commercial and industrial temperature ranges green (pb/halide-free) packaging option 1. description the at28c010 is a high-performance elec trically-erasable and programmable read- only memory. its 1 megabit of memory is organized as 131,072 words by 8 bits. man- ufactured with atmel?s advanced nonvolatile cmos technology, the device offers access times to 120 ns with power dissipation of just 220 mw. when the device is deselected, the cmos standby current is less than 200 a. the at28c010 is accessed like a static ra m for the read or write cycle without the need for external components. the device contains a 128-byte page register to allow writing of up to 128 bytes simultaneously. during a write cycle, the address and 1 to 128 bytes of data are internally latched, freeing the address and data bus for other operations. following the initiation of a write cycle, the device will automatically write the latched data using an internal contro l timer. the end of a write cycle can be detected by data polling of i/o7. once the end of a write cycle has been detected a new access for a read or write can begin. atmel?s 28c010 has additional features to ensure high quality and manufacturability. the device utilizes internal error correction for extended endurance and improved data retention characteristics. an optional software data protection mechanism is available to guard against i nadvertent writes. the devic e also includes an extra 128 bytes of eeprom for device identification or tracking. 1-megabit (128k x 8) paged parallel eeprom at28c010 0353f?peepr?04/05
2 0353f?peepr?04/05 at28c010 2.1 32-lead tsop top view 2.2 32-lead pdip top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 nc we vcc nc a16 a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we nc a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 2.3 32-lead plcc top view note: plcc package pin 1 is don?t connect. 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 a16 dc vcc we nc 2. pin configurations pin name function a0 - a16 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect dc don?t connect
3 0353f?peepr?04/05 at28c010 3. block diagram 4. device operation 4.1 read the at28c010 is accessed like a static ram. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state when either ce or oe is high. this dual-line control gives designers flexibility in preventing bus contention in their system. 4.2 byte write a low pulse on the we or ce input with ce or we low (respectively) and oe high initiates a write cycle. the address is latched on the falling edge of ce or we , whichever occurs last. the data is latched by the first rising edge of ce or we . once a byte write has been started it will automatically time itself to completion. once a programming operation has been initiated and for the duration of t wc , a read operation will effectively be a polling operation. 4.3 page write the page write operation of the at28c010 allows 1 to 128 bytes of data to be written into the device during a single internal programming perio d. a page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 127 additional bytes. each successive byte must be written within 150 s (t blc ) of the previous byte. if the t blc limit is exceeded the at28c010 will cease accepting data and commence the internal programming operation. all bytes during a page write operation must reside on the same page as defined by the state of the a7 - a16 inputs. for each we high to low transition during the page write operation, a7 - a16 must be the same. the a0 to a6 inputs are used to specify which bytes within the page are to be written. the bytes may be loaded in any order and may be altered within the same load period. only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 4.4 data polling the at28c010 features data polling to indicate the end of a write cycle. during a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on i/o 7 . once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. data polling may begin at anytime during the write cycle.
4 0353f?peepr?04/05 at28c010 4.5 toggle bit in addition to data polling the at28c010 provides another method for determining the end of a write cycle. during the write operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the write has completed, i/o6 will stop tog- gling and valid data will be read. reading the toggle bit may begin at any time during the write cycle. 4.6 data protection if precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. atmel has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.6.1 hardware protection hardware features protect against inadvertent writes to the at28c010 in the following ways: (a) v cc sense ? if v cc is below 3.8v (typical) the write function is inhibited; (b) v cc power-on delay ? once v cc has reached 3.8v the device will automatically time out 5 ms (typical) before allowing a write; (c) write inhibit ? holding any one of oe low, ce high or we high inhibits write cycles; and (d) noise filter?pulses of less than 15 ns (typical) on the we or ce inputs will not initiate a write cycle. 4.6.2 software data protection a software controlled data protection feature has been implemented on the at28c010. when enabled, the software data protection (sdp), will prevent inadvertent writes. the sdp feature may be enabled or disabled by the user; the at28c010 is shipped from atmel with sdp disabled. sdp is enabled by the host system issuing a seri es of three write commands; three specific bytes of data are written to three specific addresses (refer to software data protection algo- rithm). after writing the 3-byte command sequence and after t wc the entire at28c010 will be protected against inadvertent write operations. it should be noted, that once protected the host may still perform a byte or page write to the at28c010. this is done by preceding the data to be written by the same 3-byte command sequence used to enable sdp. once set, sdp will remain active unless the disable command sequence is issued. power transitions do not disable sdp and sdp will protect the at28c010 during power-up and power-down conditions. all command sequences must conform to the page write timing spec- ifications. the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. after setting sdp, any attempt to write to the device without the 3-byte command sequence will start the internal write timers. no data will be written to the device; however, for the dura- tion of t wc , read operations will effectively be polling operations. 4.7 device identification an extra 128 bytes of eeprom memory are available to the user for device identification. by raising a9 to 12v 0.5v and using address locations 1ff80h to 1ffffh the bytes may be written to or read from in the same manner as the regular memory array. 4.8 optional chip erase mode the entire device can be erased using a 6-byte software code. please see software chip erase application note for details.
5 0353f?peepr?04/05 at28c010 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 5. dc and ac operating range at28c010-12 at28c010-15 at28c010-20 operating temperature (case) com. 0c - 70c 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c -40c - 85c v cc power supply 5v 10% 5v 10% 5v 10% 6. operating modes mode ce oe we i/o read v il v il v ih d out write (2) v il v ih v il d in standby/write inhibit v ih x (1) xhigh z write inhibit x x v ih write inhibit x v il x output disable x v ih xhigh z 7. absolute maximum ratings* temperature under bias................................ -55c to +125c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability storage temperature ..................................... -65c to +150c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe and a9 with respect to ground ...................................-0.6v to +13.5v 8. dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc + 1v 10 a i lo output leakage current v i/o = 0v to v cc 10 a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc + 1v 200 a i sb2 v cc standby current ttl ce = 2.0v to v cc + 1v 3 ma i cc v cc active current f = 5 mhz; i out = 0 ma 40 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 a 2.4 v v oh2 output high voltage cmos i oh = -100 a; v cc = 4.5v 4.2 v
6 0353f?peepr?04/05 at28c010 10. ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (c l = 5 pf). 4. this parameter is characterized and is not 100% tested. 9. ac read characteristics symbol parameter at28c010-12 at28c010-15 at28c010-20 units min max min max min max t acc address to output delay 120 150 200 ns t ce (1) ce to output delay 120 150 200 ns t oe (2) oe to output delay 0 50 0 55 0 55 ns t df (3)(4) ce or oe to output float 0 50 0 55 0 55 ns t oh output hold from oe , ce or address, whichever occurred first 000ns
7 0353f?peepr?04/05 at28c010 11. input test waveforms and measurement level 12. output test load note: 1. this parameter is characterized and is not 100% tested. t r , t f < 5 ns 13. pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 410pfv in = 0v c out 812pfv out = 0v
8 0353f?peepr?04/05 at28c010 15. ac write waveforms 15.1 we controlled 15.2 ce controlled 14. ac write characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce ) 100 ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns
9 0353f?peepr?04/05 at28c010 17. page mode write waveforms (1)(2) notes: 1. a7 through a16 must specify the same page address during each high to low transition of we (or ce ). 2. oe must be high only when we and ce are both low. 18. chip erase waveforms 16. page mode characteristics symbol parameter min max units t wc write cycle time 10 ms t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 100 ns t blc byte load cycle time 150 s t wph write pulse width high 50 ns t s = 5 sec (min.) t w = t h = 10 msec (min.) v h = 12.0v 0.5v
10 0353f?peepr?04/05 at28c010 19. software data protection enable algorithm (1) notes: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. write protect state will be activated at end of write even if no other data is loaded. 3. write protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 128 bytes of data are loaded. load data aa to address 5555 load data 55 to address 2aaa load data a0 to address 5555 load data xx to any address (4) load last byte to last address enter data protect state writes enabled (2) 20. software data protection disable algorithm (1) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 20 to address 5555 load data xx to any address (4) load last byte to last address load data 55 to address 2aaa exit data protect state (3) 21. software protected write cycle waveforms (1)(2)(3) notes: 1. a0 through a14 must conform to the addressing sequence for the first 3 bytes as shown above. 2. after the command sequence has been issued and a page write operation follows, the page address inputs (a7 - a16) must be the same for each high to low transition of we (or ce ). 3. oe must be high only when we and ce are both low.
11 0353f?peepr?04/05 at28c010 notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. 23. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see ac read characteristics. 25. toggle bit waveforms notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. 22. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns 24. toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
12 0353f?peepr?04/05 at28c010 26. ordering information (1) note: 1. see ?valid part numbers? on page 13 . 26.1 standard package t acc (ns) i cc (ma) ordering code package operation range active standby 120 40 0.2 at28c010(e)-12jc at28c010(e)-12pc at28c010(e)-12tc 32j 32p6 32t commercial (0 to 70 c) 40 0.2 at28c010(e)-12ji at28c010(e)-12pi at28c010(e)-12ti 32j 32p6 32t industrial (-40 to 85 c) 150 40 0.2 at28c010(e)-15jc at28c010(e)-15pc at28c010(e)-15tc 32j 32p6 32t commercial (0 to 70 c) 40 0.2 at28c010(e)-15ji at28c010(e)-15pi at28c010(e)-15ti 32j 32p6 32t industrial (-40 to 85 c) 200 40 0.2 at28c010(e)-20jc at28c010(e)-20pc at28c010(e)-20tc 32j 32p6 32t commercial (0 to 70 c) 40 0.2 at28c010(e)-20ji at28c010(e)-20pi at28c010(e)-20ti 32j 32p6 32t industrial (-40 to 85 c) 26.2 green package option (pb/halide-free) t acc (ns) i cc (ma) ordering code package operation range active standby 120 40 0.2 at28c010-12ju at28c010-12tu 32j 32t industrial (-40 to 85 c) 150 40 0.2 at28c010-15ju at28c010-15tu 32j 32t industrial (-40 to 85 c) package type 32j 32-lead, plastic j-leaded chip carrier (plcc) 32p6 32-lead, 0.600" wide, plastic dual inline package (pdip) 32t 32-lead, plastic thin small outline package (tsop) w die options blank standard device: endurance = 10k write cycles; write time = 10 ms e high-endurance option: endurance = 100k write cycles
13 0353f?peepr?04/05 at28c010 27. valid part numbers the following table lists standard atmel products that can be ordered. device numbers speed package and temperature combinations at28c010 12 jc, ji, ju, pc, pi, tc, ti, tu at28c010e 12 jc, ji, pc, pi, tc, ti at28c010 15 jc, ji, ju, pc, pi, tc, ti, tu at28c010e 15 jc, ji, pc, pi, tc, ti at28c010 20 jc, ji, pc, pi, tc, ti at28c010e 20 jc, ji, pc, pi, tc, ti at28c010 -w 28. die products reference section: parallel eeprom die products
14 0353f?peepr?04/05 at28c010 29. packaging information 29.1 32j ? plcc drawing no. rev. 2325 orchard parkway san jose, ca 95131 r title 32j , 32-lead, plastic j-leaded chip carrier (plcc) b 32j 10/04/01 1.14(0.045) x 45? pin no. 1 identifier 1.14(0.045) x 45? 0.51(0.020)max 0.318(0.0125) 0.191(0.0075) a2 45? max (3x) a a1 b1 e2 b e e1 e d1 d d2 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference ms-016, variation ae. 2. dimensions d1 and e1 do not include mold protrusion. allowable protrusion is .010"(0.254 mm) per side. dimension d1 and e1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. lead coplanarity is 0.004" (0.102 mm) maximum. a 3.175 ? 3.556 a1 1.524 ? 2.413 a2 0.381 ? ? d 12.319 ? 12.573 d1 11.354 ? 11.506 note 2 d2 9.906 ? 10.922 e 14.859 ? 15.113 e1 13.894 ? 14.046 note 2 e2 12.471 ? 13.487 b 0.660 ? 0.813 b1 0.330 ? 0.533 e 1.270 typ
15 0353f?peepr?04/05 at28c010 29.2 32p6 ? pdip 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32p6 , 32-lead (0.600"/15.24 mm wide) plastic dual inline package (pdip) b 32p6 09/28/01 pin 1 e1 a1 b ref e b1 c l seating plane a 0o ~ 15o d e eb common dimensions (unit of measure = mm) symbol min nom max note a ? ? 4.826 a1 0.381 ? ? d 41.783 ? 42.291 note 1 e 15.240 ? 15.875 e1 13.462 ? 13.970 note 1 b 0.356 ? 0.559 b1 1.041 ? 1.651 l 3.048 ? 3.556 c 0.203 ? 0.381 eb 15.494 ? 17.526 e 2.540 typ note: 1. dimensions d and e1 do not include mold flash or protrusion. mold flash or protrusion shall not exceed 0.25 mm (0.010").
16 0353f?peepr?04/05 at28c010 29.3 32t ? tsop 2325 orchard parkway san jose, ca 95131 title drawing no. r rev. 32t , 32-lead (8 x 20 mm package) plastic thin small outline package, type i (tsop) b 32t 10/18/01 pin 1 d1 d pin 1 identifier b e e a a1 a2 0o ~ 8o c l gage plane seating plane l1 common dimensions (unit of measure = mm) symbol min nom max note notes: 1. this package conforms to jedec reference mo-142, variation bd. 2. dimensions d1 and e do not include mold protrusion. allowable protrusion on e is 0.15 mm per side and on d1 is 0.25 mm per side. 3. lead coplanarity is 0.10 mm maximum. a ? ? 1.20 a1 0.05 ? 0.15 a2 0.95 1.00 1.05 d 19.80 20.00 20.20 d1 18.30 18.40 18.50 note 2 e 7.90 8.00 8.10 note 2 l 0.50 0.60 0.70 l1 0.25 basic b 0.17 0.22 0.27 c 0.10 ? 0.21 e 0.50 basic
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